Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

被引：16

作者：

Fernandez, Cristina ^{[1
]}

Rodriguez, Noel ^{[1
]}

Ohata, Akiko ^{[2
]}

Gamiz, Francisco ^{[1
]}

Andrieu, Francois ^{[3
]}

Fenouillet-Beranger, Claire ^{[4
]}

Faynot, Olivier ^{[3
]}

Cristoloveanu, Sorin ^{[2
]}

机构：

[1] Univ Granada, Dept Elect, E-18071 Granada, Spain

[2] Minatec, Grenoble Inst Technol, IMEP LAHC, F-38016 Grenoble, France

[3] CEA LETI Minatec, F-38054 Grenoble, France

[4] STMicroelectronics, F-38926 Crolles, France

来源：

IEEE ELECTRON DEVICE LETTERS | 2013年 / 34卷 / 07期

关键词：

Carrier mobility; effective field; fully depleted silicon-on-insulator (FD-SOI) MOSFETs; ground plane; multibranch mobility; return point; threshold voltage; CHANNEL;

D O I：

10.1109/LED.2013.2264045

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ground-plane (GP) biasing in fully depleted siliconon-insulator (FD-SOI) MOSFETs allows not only the tuning of the threshold voltage, but also the mobility improvement. We study the carrier mobility enhancement by introducing the return point (or minimum value) of the effective field. This parameter defines the optimum GP bias condition to maximize the mobility gain. Different regions of operation can be discriminated according to the monotonic increase or decrease of the effective field with the front-gate bias. For large mobility enhancement, the return point voltage V-ret is adjusted via GP bias such as to exceed the threshold voltage. Experimental results show mobility gains over 70% in SOI MOSFETs with ultrathin buried oxide (10 nm) and Si film (8 nm).

引用

页码：840 / 842

页数：3

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