The floating potential approach to the characterization of capacitive effects in high-speed interconnects

Capacitive coupling between high speed interconnects may cause signal degradation in high density integrated circuits (ICs) and printed circuit boards (PCBs). The usual approach to the electrical characterization of interconnects is to obtain the capacitance matrix by computing charge densities from an integral equation. The latter yields dense, non-symmetric matrices and is inadequate for complex geometries and materials. Finite element methods (FEMs) yield symmetric sparse matrices but differentiation of the solution is undesirable and the more accurate energy-based calculation of capacitances is a lengthy process. A novel approach to capacitance matrix computation based on the concept of floating potentials (FPs) is introduced. This approach obviates the need to differentiate the solution and is more economical than the energy approach.