Optimization of n- and p-type TFETs Integrated on the Same InAs/AlxGa1-xSb Technology Platform

被引：44

作者：

Baravelli, Emanuele ^{[1
,2
]}

Gnani, Elena ^{[1
,2
]}

Grassi, Roberto ^{[1
,2
]}

Gnudi, Antonio ^{[1
,2
]}

Reggiani, Susanna ^{[1
,2
]}

Baccarani, Giorgio ^{[1
,2
]}

机构：

[1] Univ Bologna, Dept Elect, I-40136 Bologna, Italy

[2] Univ Bologna, Adv Res Ctr Elect Syst, I-40136 Bologna, Italy

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2014年 / 61卷 / 01期

关键词：

III-V materials; heterojunction; subthreshold slope (SS); TFET; FIELD-EFFECT TRANSISTORS; TUNNEL; VOLTAGE; GATE; FETS;

D O I：

10.1109/TED.2013.2289739

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Design of a suitable technology platform is carried out in this paper for co-integration of simultaneously optimized n- and p-type tunnel field-effect transistors (TFETs). InAs/AlxGa1-xSb heterostructures are considered, and a 3-D full-quantum simulation approach is adopted to investigate the combined effect of Al mole fraction x and transverse quantization on band lineups at the heterojunction. Design optimization leads to a TFET pair with similar dimensions and feasible aspect ratios realized on the same InAs/Al0.05Ga0.95Sb platform. These devices exhibit average subthreshold slopes below 60 mV/dec and relatively high ON-currents of 270 (n-TFET) and 120 mu A/mu m (p-TFET) at a low-supply voltage V-DD = 0.4 V. Combined ON-and OFF-state performance of the proposed technology platform is expected to be compatible with low operating power applications, while potential candidates for low standby power scenarios are obtained by reducing TFET cross sections from 10 to 7 nm.

引用

页码：178 / 185

页数：8

共 24 条

[1] Atomic-layer-deposited tantalum silicate as a gate dielectric for III-V MOS devices
Adelmann, C.
Lin, D.
Nyns, L.
Schepers, B.
Delabie, A.
Van Elshocht, S.
Caymax, M.
[J]. MICROELECTRONIC ENGINEERING, 2011, 88 (07) : 1098 - 1100
[2] [Anonymous], 2010, ISR 2010 41 INT S RO
[3] Baravelli E, 2013, PROC EUR S-STATE DEV, P69, DOI 10.1109/ESSDERC.2013.6818821
[4] Baravelli E, 2013, IEEE DEVICE RES CONF, P67, DOI 10.1109/DRC.2013.6633796
[5] Threshold voltage in Tunnel FETs: physical definition, extraction, scaling and impact on IC design
Boucart, Kathy
Ionescu, Adrian M.
[J]. ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 299 - 302
[6] Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec
Choi, Woo Young
Park, Byung-Gook
Lee, Jong Duk
Liu, Tsu-Jae King
[J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) : 743 - 745
[7] Datta S., 2010, P 20 CS MANTECH C MA, P203
[8] Elimination of spurious solutions from eight-band k center dot p theory
Foreman, BA
[J]. PHYSICAL REVIEW B, 1997, 56 (20): : 12748 - 12751
[9] Heterojunction Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current
Ganapathi, Kartik
Salahuddin, Sayeef
[J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (05) : 689 - 691
[10] Effects of high-κ (HfO2) gate dielectrics in double-gate and cylindrical-nanowire FETs scaled to the ultimate technology nodes
Gnani, Elena
Reggiani, Susanna
Rudan, Massimo
Baccarani, Giorgio
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2007, 6 (01) : 90 - 96

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