Electromigration Test on Void Formation and Failure Mechanism of FCBGA Lead-Free Solder Joints

The effect of electromigration (EM) on void formation and the failure mechanism of flip chip ball grid array (FCBGA) packages under a current density of 1.10(4) A/cm(2) and an environmental temperature of 150 degrees C was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package. scanning electron microscope (SEM) was employed to observe in situ microstructural changes, intermetallic compound (IMC) growth, and failure modes. All samples exhibited a similar failure,, attributed mainly to void occupation along under bump metallization (UBM)/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they coexisted in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1.10(4) A/cm(2) was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150 degrees C crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with copper-organic solderable preservative (Cu-OSP) after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test.