Optimized architecture and design of an output-queued CMOS switch chip

Traditional improvements in packet switch architecture aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory speed requirements and the complexity of wiring needed to connect these memories. Using a property of the combined shared memory and virtual output queuing switch architecture and a property of SRAMs, a new architecture is derived that enables construction of a terabit class switch fabric.