An MICS band frequency synthesizer using active inductor and auto-calibration scheme

被引：4

作者：

Huang, Hong-Yi ^{[1
]}

Wu, Chun-Chieh ^{[2
]}

Luo, Ching-Hsing ^{[2
]}

机构：

[1] Natl Taipei Univ, Grad Inst Elect Engn, Taipei, Taiwan

[2] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

来源：

MICROELECTRONICS JOURNAL | 2012年 / 43卷 / 08期

关键词：

Voltage control oscillator; Fractional-N PLL; Active inductor; Auto calibration; VCO;

D O I：

10.1016/j.mejo.2011.09.012

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An MICS band fractional-N frequency synthesizer using active inductors and auto-calibration technology is presented in this work. The active inductors and capacitors of the loop filter were implemented with MOSFET for decreasing the phase noise and silicon area. Moreover, the proposed auto-calibration technique would reduce and overcome the effect of voltage, temperature, and process variations. This chip was fabricated in 0.18 mu m CMOS process. The measurement results show that the proposed 402-405 fractional-N PLL occupies a core area of 450 x 385 mu m(2). The phase noise is -105.5 dBc/Hz at 1 MHz. The power consumption is 5.13 mW at 402 MHz. (C) 2011 Elsevier Ltd. All rights reserved.

引用

页码：592 / 599

页数：8

共 20 条

[1] A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs [J].

Bonfanti, A ;

Levantino, S ;

Samori, C ;

Lacaita, AL .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (03) :481-488

[2] A 100 MHz-1 GHz adaptive bandwidth PLL using TDC technique [J].

Cheng, Kuo-Hsing ;

Lo, Yu-Lung ;

Lai, Ching-Wen ;

Yang, Wei-Bin .

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, :1163-+

[3] Gain-boosting charge pump for current matching in phase-locked loop [J].

Choi, Young-Shig ;

Han, Dae-Hyun .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (10) :1022-1025

[4] On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity [J].

De Muer, B ;

Steyaert, MSJ .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2003, 50 (11) :784-793

[5]

Fan Bing, 2008, IEEE INT C SOL STAT, P1929

[6] Mathematical analysis of a prime modulus quantizer MASH digital delta-sigma modulator [J].

Hosseini, Kaveh ;

Kennedy, Michael Peter .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (12) :1105-1109

[7]

Jhou W.J., 2006, THESIS NATL CHUNG YU

[8] Low phase noise and Fast locking PLL Frequency Synthesizer for a 915MHz ISM Band [J].

Kim, Seung-Hoon ;

Cho, Sang-Bock .

2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, :592-595

[9] An agile VCO frequency-calibration technique for a 10-GHz CMOS PLL [J].

Lin, Tsung-Hsien ;

Lai, Yu-Jen .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (02) :340-349

[10]

Lin W.J. Tsung-Hsien, 2001, IEEE J SOLID-ST CIRC, V36, P424

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