On performance scaling and speed of junctionless transistors

被引：28

作者：

Koukab, A. ^{[1
]}

Jazaeri, F. ^{[1
]}

Sallese, J. -M. ^{[1
]}

机构：

[1] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

来源：

SOLID-STATE ELECTRONICS | 2013年 / 79卷

关键词：

Junctionless; Gated resistor; VeSFET; MOSFET; Delay; Performance roadmap; NANOWIRE TRANSISTORS;

D O I：

10.1016/j.sse.2012.08.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A prospective study of the junctionless transistors (JLTs) scaling performances based both on TCAD and analytical evaluations of the intrinsic delay after considering on/off voltage constraints is proposed. The tradeoffs between speed and switching power performances in regard to the JLT parameters are analyzed. It is demonstrated that JLTs performances in terms of speed are very similar to that of regular bulk MOSFETs, and that increasing the drive current and speed still needs to shrink the gate oxide just as in MOSFETs. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：18 / 21

页数：4

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