Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

被引：19

作者：

Ke, M. ^{[1
,2
]}

Yu, X. ^{[1
,2
]}

Zhang, R. ^{[1
]}

Kang, J. ^{[1
,2
]}

Chang, C. ^{[1
,2
]}

Takenaka, M. ^{[1
,2
]}

Takagi, S. ^{[1
,2
]}

机构：

[1] Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1138656, Japan

[2] JST CREST, Tokyo, Japan

来源：

MICROELECTRONIC ENGINEERING | 2015年 / 147卷

关键词：

Germanium; High-k dielectrics; Hysteresis; Slow trap density; Plasma post oxidation; MOS interface;

D O I：

10.1016/j.mee.2015.04.079

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (D-it) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO3/GeOx/Ge MOS interface, formed by atomic layer deposition (ALD) AlYO3/Ge MOS structures with plasma post oxidation (PPO). Reduction in D-it by PPO is found for AlYO3/Ge system. A 1.5-nm-thick AlYO3/GeOx/Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al2O3/GeO5/Ge interface and the Y2O3/GeO5/Ge interface. Deposition of any high-k films on the AlYO3/GeOx/Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO3. (C) 2015 Elsevier B.V. All rights reserved.

引用

页码：244 / 248

页数：5

共 12 条

[1]

Bethge O., 2014, ECS T, P69

[2] Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks [J].

Franco, J. ;

Kaczer, B. ;

Roussel, Ph. J. ;

Mitard, J. ;

Sioncke, S. ;

Witters, L. ;

Mertens, H. ;

Grasser, T. ;

Groeseneken, G. .

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,

[3]

Groeseneken G., 2014, IEDM, P828

[4]

Lee C. H., 2013, 2013 Symposium on VLSI Technology, pT28

[5]

Lee C.H., 2013, Proc. IEEE IEDM, P40, DOI [10.1109/IEDM.2013, DOI 10.1109/IEDM.2013]

[6]

Lu C., 2014, SSDM, P708

[7] Maintaining the benefits of CMOS scaling when scaling bogs down [J].

Nowak, EJ .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2002, 46 (2-3) :169-180

[8] Impact of plasma post oxidation temperature on interface trap density and roughness at GeOx/Ge interfaces [J].

Zhang, R. ;

Lin, J. C. ;

Yu, X. ;

Takenaka, M. ;

Takagi, S. .

MICROELECTRONIC ENGINEERING, 2013, 109 :97-100

[9]

Zhang R., 2011, Appl. Phys. Lett., V98

[10] High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Postoxidation [J].

Zhang, Rui ;

Huang, Po-Chin ;

Lin, Ju-Chin ;

Taoka, Noriyuki ;

Takenaka, Mitsuru ;

Takagi, Shinichi .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (03) :927-934

← 1 2 →