Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal-Oxide-Semiconductor Field-Effect Transistors

被引:3
作者
Yoon, JongChul [1 ]
Hiroki, Akira [1 ]
Kobayashi, Kazutoshi [1 ]
机构
[1] Kyoto Inst Technol, Grad Sch Sci & Technol, Kyoto 6068585, Japan
关键词
CURRENT MODEL; EXTENSION; FINFET; IMPACT;
D O I
10.7567/JJAP.52.071302
中图分类号
O59 [应用物理学];
学科分类号
摘要
The structural dependence of series-resistance effects on the saturation current is investigated in sub-20 nm metal-oxide-semiconductor field-effect transistors (MOSFETs). For planer bulk, silicon-on-insulator (SOI), and multi gate (MG) MOSFETs, the reduction rate of the saturation current is calculated using an analytical current model in high-performance (HP), low-operating-power (LOP), and low-standby-power (LSTP) technologies. In HP technology, the reduction rates are 29.0, 25.3, and 22.1% for bulk, SOI, and MG MOSFETs, respectively. In LOP technology, the reduction rates are 23.8, 21.5, and 20.7% for bulk, SOI, and MG MOSFETs, respectively. In LSTP technology, the reduction rates are about 17% for all devices. In HP technology, the ratio of the series resistance to the channel resistance is the dominant factor for the reduction rate. In LOP technology, the ratio of the over drive voltage to the supply voltage is the dominant factor. In LSTP technology, both the resistance and voltage ratios are the dominant factors. (C) 2013 The Japan Society of Applied Physics
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页数:5
相关论文
共 27 条
[1]   A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch [J].
Basker, V. S. ;
Standaert, T. ;
Kawasaki, H. ;
Yeh, C. -C. ;
Maitra, K. ;
Yamashita, T. ;
Faltermeier, J. ;
Adhikari, H. ;
Jagannathan, H. ;
Wang, J. ;
Sunamura, H. ;
Kanakasabapathy, S. ;
Schmitz, S. ;
Cummings, J. ;
Inada, A. ;
Lin, C. -H. ;
Kulkarni, P. ;
Zhu, Y. ;
Kuss, J. ;
Yamamoto, T. ;
Kumar, A. ;
Wahl, J. ;
Yagishita, A. ;
Edge, L. F. ;
Kim, R. H. ;
Mclellan, E. ;
Holmes, S. J. ;
Johnson, R. C. ;
Levin, T. ;
Demarest, J. ;
Hane, M. ;
Takayanagi, M. ;
Colburn, M. ;
Paruchuri, V. K. ;
Miller, R. J. ;
Bu, H. ;
Doris, B. ;
McHerron, D. ;
Leobandung, E. ;
O'Neill, J. .
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, :19-+
[2]  
Bohr M., 2011, IEDM, P11
[3]  
Chang J. B., 2002, S VLSI TECHN, P12
[4]   An accurate semi-empirical saturation drain current model for LDD N-MOSFET [J].
Chen, K ;
Wann, HC ;
Duster, J ;
Pramanik, D ;
Nariani, S ;
Ko, PK ;
Hu, C .
IEEE ELECTRON DEVICE LETTERS, 1996, 17 (03) :145-147
[5]   The impact of device scaling and power supply change on CMOS gate performance [J].
Chen, K ;
Wann, HC ;
Ko, PK ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 1996, 17 (05) :202-204
[6]   Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's [J].
Choi, CH ;
Goo, JS ;
Yu, ZP ;
Dutton, RW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (03) :655-658
[7]   Analysis of the parasitic S/D resistance in multiple-gate FETs [J].
Dixit, A ;
Kottantharayil, A ;
Collaert, N ;
Goodwin, M ;
Jurezak, M ;
De Meyer, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (06) :1132-1140
[8]   A NEW APPROACH TO DETERMINE THE EFFECTIVE CHANNEL-LENGTH AND THE DRAIN-AND-SOURCE SERIES RESISTANCE OF MINIATURIZED MOSFETS [J].
GUO, JC ;
CHUNG, SSS ;
HSU, CCH .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (10) :1811-1818
[9]   IMPACT OF THE VERTICAL SOI DELTA STRUCTURE ON PLANAR DEVICE TECHNOLOGY [J].
HISAMOTO, D ;
KAGA, T ;
TAKEDA, E .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (06) :1419-1424
[10]  
Hisamoto D, 2000, IEEE T ELECTRON DEV, V47, P2320, DOI 10.1109/16.887014