Comparison and design of dynamic comparator in 180nm SCL technology for low power and high speed Flash ADC

被引：2

作者：

Hussain, Sarfraz ^{[1
]}

Kumar, Rajesh ^{[1
]}

Trivedi, Gaurav ^{[2
]}

机构：

[1] NERIST, Dept ECE, Nirjuli, Arunachal Prade, India

[2] IIT Guwahati, Dept EEE, Gauhati, Assam, India

来源：

2017 3RD IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS) | 2017年

关键词：

dynamic comparator; high speed; latch; low-power; flash ADC;

D O I：

10.1109/iNIS.2017.37

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A modified dynamic comparator is proposed and compared in this paper. A dynamic comparator consists of a low gain amplifier connected to a latch circuit. The inputs are amplified during the evaluation period and the outputs are latched during the regeneration time. The proposed dynamic comparator is fast and consumes less power. At a clock frequency of 1.25GHz and 100mV.Vin, the delay is 176.71ps and average power consumption is 119.81 mu W for a supply voltage of 1.8V. The calculated maximum PDP is 24.53 f. The proposed dynamic comparator is suitable for an efficient low power and high speed Flash ADC. The circuits are simulated in cadence virtuoso spectre with 180nm SCL technology.

引用

页码：139 / 144

页数：6

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