Combinational Logic Design Using Six-Terminal NEM Relays

被引：25

作者：

Lee, Daesung ^{[1
]}

Lee, W. Scott ^{[1
]}

Chen, Chen ^{[1
]}

Fallah, Farzan ^{[1
]}

Provine, J. ^{[1
]}

Chong, Soogine ^{[1
]}

Watkins, John ^{[1
]}

Howe, Roger T. ^{[1
]}

Wong, H. -S. Philip ^{[1
]}

Mitra, Subhasish ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2013年 / 32卷 / 05期

基金：

美国国家科学基金会;

关键词：

Binary decision diagram; logic synthesis; nanoelectromechanical (NEM) relays; nanotechnology; NANOELECTROMECHANICAL LOGIC; CMOS;

D O I：

10.1109/TCAD.2012.2232707

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.

引用

页码：653 / 666

页数：14

共 25 条

[1] Design considerations for complementary nanoelectromechanical logic gates
Akarvardar, K.
Elata, D.
Parsa, R.
Wan, G. C.
Yoo, K.
Provine, J.
Peurnans, P.
Howe, R. T.
Wong, H-S. P.
[J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 299 - 302
[2] Nanoelectromechanical Logic and Memory Devices
Akarvardar, Kerem
Wong, H. -S. Philip
[J]. ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 49 - 59
[3] AKERS SB, 1978, IEEE T COMPUT, V27, P509, DOI 10.1109/TC.1978.1675141
[4] [Anonymous], PUBLIC SOFTWARE
[5] [Anonymous], NANG 45 NM LIB
[6] [Anonymous], IBM TECH DISCLOSURE
[7] Brayton R. K., 1996, Computer Aided Verification. 8th International Conference, CAV '96. Proceedings, P428
[8] BRYANT RE, 1986, IEEE T COMPUT, V35, P677, DOI 10.1109/TC.1986.1676819
[9] Chen Fred, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), P750, DOI 10.1109/ICCAD.2008.4681660
[10] Congguang Yang, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), P626, DOI 10.1109/ICCD.1999.808607

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