Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions

被引：271

作者：

Matsunaga, Shoun

Hayakawa, Jun ^{[2
]}

Ikeda, Shoji ^{[1
]}

Miura, Katsuya ^{[1
,2
]}

Hasegawa, Haruhiro ^{[1
]}

Endoh, Tetsuo ^{[3
]}

Ohno, Hideo ^{[1
]}

Hanyu, Takahiro ^{[1
]}

机构：

[1] Tohoku Univ, Elect Commun Res Inst, Lab Nanoelect & Spintron, Sendai, Miyagi 9808577, Japan

[2] Hitachi Adv Res Lab, Tokyo 1858601, Japan

[3] Tohoku Univ, Interdisciplinary Res Ctr, Sendai, Miyagi 9808578, Japan

来源：

APPLIED PHYSICS EXPRESS | 2008年 / 1卷 / 09期

关键词：

D O I：

10.1143/APEX.1.091301

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 mu m complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed. (C) 2008 The Japan Society of Applied Physics.

引用

收藏

页码：0913011 / 0913013

页数：3

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