Enhancing performance of HW/SW cosimulation and coemulation by reducing communication overhead

被引:12
作者
Chung, MK [1 ]
Kyung, CM [1 ]
机构
[1] Korea Adv Inst Sci & Technol, VLSI Syst Lab, Taejon 305701, South Korea
关键词
simulation performance; system-level verification; cosimulation; coemulation; heterogeneous simulation environment;
D O I
10.1109/TC.2006.24
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To reduce the amount of communication in this heterogeneous simulation environment, we propose novel methods to find a time interval during which there are no transactions among simulators based on a dynamic prediction of transaction occurrence time for both software and hardware models. We also propose a simulator scheduling algorithm which allows the simulator to work alone without interaction with others when there is no transaction. By so doing, we reduced the amount of pure communication by a factor of 15 to 67 and, as a result, achieved a speed-up factor of 4 to 40 compared to existing lock-step simulation, as shown by experimental results with various application examples.
引用
收藏
页码:125 / 136
页数:12
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