Rapid-prototyping of high-performance RISC cores with VHDL

被引：4

作者：

Bautista, T

Marrero, G

Carballo, PP

Nunez, A

机构：

来源：

VHDL INTERNATIONAL USERS' FORUM, PROCEEDINGS | 1997年

关键词：

D O I：

10.1109/VIUF.1997.623928

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present some experiences we have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of high-performance embeddable cores.

引用

页码：43 / 52

页数：4