A 10-bit 100-MS/s 2b/cycle-Assisted SAR ADC in 180nm CMOS

被引：0

作者：

Chung, Yung-Hui ^{[1
]}

Tseng, Hua-Wei ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, EE601-9,43,Sec 4,Keelung Rd, Taipei, Taiwan

来源：

2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2017年

关键词：

A/D converter (ADC); D/A converter (DAC); successive approximation register (SAR); 2b/cycle;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.

引用

页数：2