The impact of multiple failure modes on estimating product field reliability

被引：22

作者：

Carulli, JM ^{[1
]}

Anderson, TJ ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Technol Dev Div, Dallas, TX 75265 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2006年 / 23卷 / 02期

关键词：

D O I：

10.1109/MDT.2006.53

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A difficulty in reliability modeling is how to capture the impact of all of the various reliability defect types. This is particularly difficult because defect signatures vary based on fab, technology maturity, and product details. This article describes the framework for addressing a multitude of reliability defects to estimate product DPPM from production burn-in and operation-life data.

引用

页码：118 / 126

页数：9

共 12 条

[1]

[Anonymous], P IEEE INT REL PHYS

[2]

Barnett TS, 2003, INT TEST CONF P, P77, DOI 10.1109/TEST.2003.1270827

[3] Extending integrated-circuit yield-models to estimate early-life reliability [J].

Barnett, TS ;

Singh, AD ;

Nelson, VP .

IEEE TRANSACTIONS ON RELIABILITY, 2003, 52 (03) :296-300

[4] Screening MinVDD Outliers using feed-forward voltage testing [J].

Madge, R ;

Goh, BH ;

Rajagopalan, V ;

Macchietto, C ;

Daasch, R ;

Schuermyer, C ;

Taylor, C ;

Turner, D .

INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, :673-682

[5] Statistical post-processing at Wafersort - An alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies. [J].

Madge, R ;

Rehani, M ;

Cota, K ;

Daasch, WR .

20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, :69-74

[6]

Nigh P, 2004, INT TEST CONF P, P309

[7]

Wolstenholme LC, 1999, RELIABILITY MODELING

[8]

[No title captured]

[9]

[No title captured]

[10]

[No title captured]

← 1 2 →