A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TELT by using the combined two methods. The ON to OFF current ratio (I-ON/I-OFF) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (g(m)) and unit-gain cutoff frequency (f(T)) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (t(phl)) and overshoot voltage (V-P) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TELT over Si-TEL,T that makes the proposed design more advantageous in the field of analog and digital applications.