Unified HW/SW Framework for Efficient System Level Simulation

被引:0
作者
Sutisna, N. [1 ]
Lanante, L., Jr. [1 ]
Nagao, Y. [1 ]
Kurosaki, M. [1 ]
Ochi, H. [1 ]
机构
[1] Kyushu Inst Technol, Dept Comp Sci & Elect, Kitakyushu, Fukuoka, Japan
来源
2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2016年
关键词
Unified HW/SW co-verification; FPGA prototyping; Hardware-In-the-Loop; MIMO Wireless System;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present unified Hardware (HW)/Software (SW) framework for efficient system level simulation of complex circuits, particularly high throughput wireless communication system. The proposed framework include a unified methodology covering both of system level simulation (e.g. MATLAB or C/C++) and physical level verification (e.g FPGA). It allows performing fast HW/SW evaluation in the context of system level performance and also covering large number of verification scenarios within acceptable time. Experimental evaluations show the example design case achieves improvement. of simulation time several orders of magnitude faster than pure software simulation and also capable to run in near real-time processing. Moreover, the proposed verification platform can be used for complete performance characterization of a MIMO wireless system under various system parameters, hardware impairments and channel model.
引用
收藏
页码:518 / 521
页数:4
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