Reliability-aware platform optimization for 3D chip multi-processors

Three-dimensional (3D) Chip Multiprocessors (CMPs) have the potential to improve communication latency as well as integration density. Nevertheless, the stacked nature of the cores introduces thermal challenges that can have severe reliability consequences. In this work, we introduce a reliability-aware platform that tries to optimize power and reliability. We achieve this by integrating a power management policy that we introduced in Kdouh and El-Rewini (ISCA 22nd International Conference on Computer Applications in Industry and Engineering (CAINE-2009), 4-6 November 2009), along with a thermal management policy, as well as a temperature-aware 3D routing algorithm. The thermal management policy is responsible for respecting different correlations between the cores. As for the temperature-aware 3D routing algorithm, it has the capability to dynamically react to the thermal constraints. Furthermore, we introduce a 3D CMP architecture that accommodates our policies. The proposed platform is evaluated using multi-threaded benchmarks in an integrated power, performance, and temperature full system simulator.