A Study of Interferences Inside an RF Switch Array in 45nm SOI CMOS

被引：0

作者：

Wang, Chenkun ^{[1
]}

Lu, Fei ^{[1
]}

Chen, Qi ^{[1
]}

Zhang, Feilong ^{[1
]}

Li, Cheng ^{[1
]}

Wang, Dawn ^{[2
]}

Wang, Albert ^{[1
]}

机构：

[1] Univ Calif Riverside, Dept Elect & Comp Engn, Riverside, CA 92521 USA

[2] Global Foundries, Santa Clara, CA USA

来源：

2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2017年

关键词：

CMOS; SOI; switch array; interference; isolation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a study of interferences inside an RF switch array, aiming to understand the design influences on interference characteristics. The 2x2 single-pole double/triple-throw (SP2T/SP3T) Tx/Rx band switch array, featuring a series-shunt topology with gate resistance and feed-forward capacitance (FFC) and covering low (699-894MHz) and high (1710-2155MHz) bands, was designed and fabricated in a 45nm SOI CMOS. The inter-band and inner-band interferences were characterized, which reveals that existing noise isolation techniques, e.g., substrate isolation and layout floor planning, are insufficient for interference reduction. It therefore calls for novel in-die interference elimination techniques.

引用

页数：3

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