Wire Sizing Regulation Algorithm for VLSI Interconnect Timing Optimization

被引：0

作者：

Wang, Xin-Sheng ^{[1
]}

Han, Liang

Liu, Xing-Chun ^{[2
]}

Yu, Ming-Yan ^{[1
,2
]}

机构：

[1] Harbin Inst Technol, Sch Astronaut, Harbin 150001, Peoples R China

[2] Harbin Inst Technol, Dept Informat & Elect Engn, Harbin, Peoples R China

来源：

2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a Modified Active Set Algorithm (MASA) in optimal wire sizing problem for VLSI interconnect timing minimization Based on the Elmore delay model, the optimal wire sizing can be formulated as a convex quadratic program, which is known to be solvable in polynomial time and derive an optimal solution. The algorithm is very efficient for arbitrary interconnect structures under the distributed Elmore delay model. The effectiveness of the algorithm is proved by the runtime compared with Active Set Algorithm.

引用

页码：410 / 412

页数：3

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