Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at V-DD < 0.17V at iso delay for the Kogge Stone adder. For example, we get 9.21% energy reduction at ferroelectric layer thickness of 3nm and 36% energy reduction for a ferroelectric layer thickness of 6nm at the iso carry path delay of 3.1 ns for an 8 not Kogge Stone adder.