Advanced DC-SF Cell Technology for 3-D NAND Flash

被引：14

作者：

Aritome, Seiichi ^{[1
,2
]}

Noh, Yoohyun ^{[1
]}

Yoo, Hyunseung ^{[1
]}

Choi, Eun Seok ^{[1
]}

Joo, Han Soo ^{[1
]}

Ahn, Youngsoo ^{[1
]}

Han, Byeongil ^{[1
]}

Chung, Sungjae ^{[1
]}

Shim, Keonsoo ^{[1
]}

Lee, Keunwoo ^{[1
]}

Kwak, Sanghyon ^{[1
]}

Shin, Sungchul ^{[1
]}

Choi, Iksoo ^{[1
]}

Nam, Sanghyuk ^{[1
]}

Cho, Gyuseog ^{[1
]}

Sheen, Dongsun ^{[1
]}

Pyi, Seungho ^{[1
]}

Choi, Jongmoo ^{[1
]}

Park, Sungkye ^{[1
]}

Kim, Jinwoong ^{[1
]}

Lee, Seokkiu ^{[1
]}

Hong, Sungjoo ^{[1
]}

Park, Sungwook ^{[1
]}

Kikkawa, Takamaro ^{[2
]}

机构：

[1] SK Hynix Inc, R&D Div, Ichon 467701, South Korea

[2] Hiroshima Univ, Res Inst Nanodevice & Bio Syst, Grad Sch Adv Sci Matter, Higashihiroshima 7398527, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2013年 / 60卷 / 04期

关键词：

Floating gate; NAND Flash; nonvolatile memory; 3-D cell;

D O I：

10.1109/TED.2013.2247606

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D NAND flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D NAND flash memories.

引用

页码：1327 / 1333

页数：7