Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology

被引：0
|
作者：
Altolaguirre, Federico A. [1 ]
Ker, Ming-Dou [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan
来源：
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT) | 2013年
关键词：
PROTECTION DESIGN;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25 degrees C, and a ESD robustness of 3kV HBM and 200V MM.
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页数：4
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