Parallel Dataflow Execution for Sequential Programs on Reconfigurable Hybrid MPSoCs

Reconfigurable hybrid multi-processor systems-on-chips (MPSoCs) are very powerful computing platforms. However, it has been quite challenging to schedule and map tasks to different function units of the MPSoCs, especially for tasks with inter-task dependencies. This paper introduces a parallel dataflow execution support, called ReArc, for the FPGA based reconfigurable hybrid MPSoCs. It constructs a hierarchical model for the high level programming with a parallel execution flow and dynamic reconfigurations. A prototype has been built on a Xilinx FPGA with a state-of-the-art software-hardware co-design paradigm. Experimental results demonstrate that ReArc could significantly facilitate researchers to construct a high-level, application oriented FPGA implementation with acceptable hardware utilizations and reconfiguration overheads.