Design of Low-power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process

被引：1

作者：

Sam, D. S. Shylu ^{[1
]}

Paul, P. Sam ^{[1
]}

Jingle, Diana Jeba ^{[2
]}

Paul, P. Mano ^{[3
]}

Samuel, Judith ^{[1
]}

Reshma, J. ^{[1
]}

Sarah, P. ^{[1
]}

Evangeline, Sudeepa G. ^{[1
]}

机构：

[1] Karunya Inst Technol & Sci, Coimbatore, India

[2] Christ Deemed Univ, Bangalore, India

[3] Alliance Univ, Bangalore, India

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS | 2022年 / 68卷 / 03期

关键词：

FLASH ADC; Low Power; Dynamic Comparator; Encoder;

D O I：

10.24425/ijet.2022.141275

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.

引用

页码：565 / 570

页数：6

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