A 51.4 Mb/s FSK Transmitter Employing a Phase Domain Digital Synthesizer with 1.5 μs Start-up for Energy Efficient Duty Cycling

被引：0

作者：

Thirunarayanan, Raghavasimhan ^{[1
,2
]}

Ruffieux, David ^{[2
]}

Scolari, Nicola ^{[2
]}

Enz, Christian ^{[1
]}

机构：

[1] EPFL, Neuchatel, Switzerland

[2] CSEM, Neuchatel, Switzerland

来源：

ESSCIRC CONFERENCE 2016 | 2016年

关键词：

Energy Efficiency; Duty Cycling; FBAR; Phase Domain Digital Synthesizer; Hybrid Requantizer;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 mu s. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced Sigma Delta noise folding.

引用

页码：129 / 132

页数：4