HIGHLY STABLE POWER EFFICIENT NOISE TOLERANT CIRCUITS FOR ANALOG AND DIGITAL SYSTEMS

被引：0

作者：

Seenuvasamurthi, S. ^{[1
]}

Nagarajan, G. ^{[1
]}

机构：

[1] Pondicherry Engn Coll, Dept ECE, Pondicherry, India

来源：

PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16) | 2016年

关键词：

Noise immunity; Switching activity; Dynamic logic; LOGIC;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Noise is an important factor in the analog and digital circuits which determine the characteristics of the system. The work aims at developing a noise robust circuit with high frequency response and the same can be implemented in a dynamic logic system with reduced number of transistor and also the dynamic logic will have the probability of signal switching activity to be low which will subsequently reduce the power of the system. The circuits have been constructed using cadence ADE and the same has been simulated with Spectre using 45nm GPDK technology. The simulation results show that the power consumption has been reduced multi-fold and the bandwidth has been increased by 10(2) Hz and the delay is reduced by 50%.

引用

页数：6

共 17 条

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