A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

被引：78

作者：

Lu, Ping ^{[1
]}

Liscidini, Antonio ^{[1
]}

Andreani, Pietro ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect Engn, I-27100 Pavia, Italy

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2012年 / 47卷 / 07期

关键词：

Gated ring oscillator; time-to-digital converter; Vernier delay line; PHASE-LOCKED LOOP; PLL;

D O I：

10.1109/JSSC.2012.2191676

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90 nm CMOS process and consumes 3 mA from 1.2 V when operating at 25 MHz. The native Vernier resolution of the TDC is 5.8 ps, while the total noise integrated over a bandwidth of 800 kHz yields an equivalent TDC resolution of 3.2 ps.

引用

页码：1626 / 1635

页数：10

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