A 2.5-V BiCMOS comparator with current-mode interpolation

被引：6

作者：

Boni, A ^{[1
]}

Morandi, C ^{[1
]}

Padoan, S ^{[1
]}

机构：

[1] Univ Parma, Dipartimento Ingn Informaz, I-43100 Parma, Italy

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 06期

关键词：

analog-to-digital (A/D) conversion; current-mode architectures; high-speed comparators; low power; low voltage;

D O I：

10.1109/4.766825

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5-V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADC's), Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8-mu m BiCMOS technology.

引用

页码：892 / 897

页数：6

共 14 条

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