Background capacitor mismatch calibration for pipelined ADC

被引：0

作者：

El-Sankary, K ^{[1
]}

Sawan, M ^{[1
]}

机构：

[1] Ecole Polytech, Dept Elect Engn, PolySTIM Neurotechnol Lab, Montreal, PQ H3C 3A7, Canada

来源：

Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new digital background calibration technique to compensate the capacitor mismatch in pipelined analog-to-digital converters (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to global gain error. A simple modification to the conventional MDAC allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC. This method does not produce any limitation of the ADC in terms of speed or input dynamic range.

引用

页码：164 / 167

页数：4

共 11 条

[1] Inherently linear capacitor error-averaging techniques for pipelined A/D conversion
Chiu, Y
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (03): : 229 - 232
[2] FETTERMAN H, 2003, Patent No. 6515611
[3] A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
Ingino, JM
Wooley, BA
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) : 1920 - 1931
[4] A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
Jamal, SM
Fu, DH
Chang, NCJ
Hurst, PJ
Lewis, SH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (12) : 1618 - 1627
[5] Explicit analysis of channel mismatch effects in time-interleaved ADC systems
Kurosawa, N
Kobayashi, H
Maruyama, K
Sugawara, H
Kobayashi, K
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2001, 48 (03) : 261 - 271
[6] A 12-B 600-KS/S DIGITALLY SELF-CALIBRATED PIPELINED ALGORITHMIC ADC
LEE, HS
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (04) : 509 - 515
[7] LIU H, 2003, P IEEE INT S CIRC SY, V1, P881
[8] A digital error-averaging technique for pipelined A/D conversion
Rombouts, P
Weyten, L
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (09): : 1321 - 1323
[9] Oversampled pipeline A/D converters with mismatch shaping
Shabra, A
Lee, HS
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (05) : 566 - 578
[10] A 12-BIT 1-MSAMPLE/S CAPACITOR ERROR-AVERAGING PIPELINED A/D CONVERTER
SONG, BS
TOMPSETT, MF
LAKSHMIKUMAR, KR
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (06) : 1324 - 1333

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