Impact of Si-Thickness on Interface and Device Properties for Si-passivated Ge pMOSFETs

被引：27
|
作者：
Martens, Koen [1 ,2 ]
Mitard, Jerome [1 ]
De Jaeger, Brice [1 ]
Meuris, Marc [1 ]
Maes, Herman [2 ]
Groeseneken, Guido [2 ]
Minucci, Franco [2 ]
Crupi, Felice [3 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, ESAT Dept, Leuven, Belgium
[3] Univ Calabria, Arcavacata Di Rende, Italy
来源：
ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2008年
关键词：
D O I：
10.1109/ESSDERC.2008.4681718
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The semiconductor-dielectric interface passivation of Ge pMOSFETs with an epitaxially grown Si-layer is studied by means of the full conductance technique. This technique resolves several issues which occur for alternative MOS-interfaces when using the 'classical' conductance technique. The observed mobility behavior as a function of Si-passivation thickness can be explained by the observed variation in interface state density. Observed threshold voltage shifts as a function of Si-passivation thickness can also be linked to the variation in interface state density with thickness.
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页码：138 / +
页数：2
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