The Impact of BTI Variations on Timing in Digital Logic Circuits

被引：27

作者：

Fang, Jianxin ^{[1
]}

Sapatnekar, Sachin S. ^{[1
]}

机构：

[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2013年 / 13卷 / 01期

基金：

美国国家科学基金会;

关键词：

Bias temperature instability (BTI); circuit reliability; process variation (PV); timing analysis; DEGRADATION; RELIABILITY; NBTI;

D O I：

10.1109/TDMR.2013.2237910

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.

引用

页码：277 / 286

页数：10

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