Efficient Fault-Tolerant Design for Parallel Matched Filters

Parallel matched filters (PMFs) are widely used in digital communication systems for efficient timing synchronization. In this brief, an efficient fault-tolerant design is proposed for PMFs. In the proposed scheme, the correlation between the different filters is used for fault detection and recovery, so that the redundant filters that are needed in existing solutions can be removed, which reduces the implementation cost. The evaluation of practically applied PMFs on an FPGA implementation shows that the proposed scheme can reduce significantly the overheads compared to existing protection methods. The proposed scheme can also be applied to other parallel processing systems with mutual correlation.