A HIGH-SPEED REVERSIBLE LOW-POWER ERROR TOLERANT ADDER

被引：0

作者：

Raheem, M. A. ^{[1
]}

Gupta, Harsh ^{[2
]}

Fatima, Kaleem ^{[1
]}

Adil, Osman ^{[1
]}

机构：

[1] Muffakham Jah Coll Engn & Technol, ECE Dept, Hyderabad, Andhra Pradesh, India

[2] ICFAI Univ, Hyderabad, Andhra Pradesh, India

来源：

2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA) | 2012年

关键词：

Error Tolerance; Reversible Logic; Quantum Cost; Accuracy; High Speed Circuits; Low Power Design; Garbage Outputs; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new reversible Error Tolerant Adder (ETA) based on the reversible Logic is proposed. RH and RS gates are the novel reversible logic gates based on which the ETA is designed. The reversible 3x3 RH gate is derived from existing 2x2 quantum gates - CNOT, Controlled-V and Controlled-V+. The reversible 3x3 RS gate consists of the existing CNOT and Peres Quantum gates. The design of the proposed reversible ETA demonstrates better power delay product (PDP) than the existing ETA's in terms of quantum cost and delay, while maintaining the minimum number of garbage outputs. In comparison with other ETAs, the current design offers a PDP improvement of 54.06%.

引用

页码：178 / 183

页数：6

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