Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

被引：58

作者：

Jung, Chul-Moon ^{[1
]}

Choi, Jun-Myung ^{[1
]}

Min, Kyeong-Sik ^{[1
]}

机构：

[1] Kookmin Univ, Sch Elect Engn, Seoul 136702, South Korea

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2012年 / 11卷 / 03期

关键词：

Complementary memristor (CM) cell; cross-point memories; memristor; passive memory array; sneak-path leakage; two-step write; MEMORY ARRAY; LOW-POWER; CIRCUIT;

D O I：

10.1109/TNANO.2012.2188302

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R-RESET/R-SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If RRESET/RSET is increased to 500, we can increase the passive array size up to 1000 x 1000 with maintaining the read sensing margin lager than 10% of V-DD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

引用

页码：611 / 618

页数：8

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