Power design challenges in deep-submicron technology

Power-efficient designs are becoming of increasing importance in the deep-submicron regime. Over the past decade, the reduction of dynamic power was the main focus in the design of power-efficient integrated circuits. However, as technology scales down, subthreshold and gate oxide leakage currents can no longer be neglected, and must be taken into account in any design. Furthermore, the delivery of power to CMOS integrated circuits is facing increasing challenges in the deep-submicron regime. This paper investigates the challenges associated with designing power-efficient circuits as well as the delivery of power.