A unified approach to constrained mapping and routing on network-on-chip architectures

被引：0

作者：

Hansson, A ^{[1
]}

Goossens, K ^{[1
]}

Radulescu, A ^{[1
]}

机构：

[1] Lund Univ, Dept Informat Technol, S-22100 Lund, Sweden

来源：

2005 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS | 2005年

关键词：

system-on-chip; network-on-chip; quality-of-service; mapping; routing;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.

引用

页码：75 / 80

页数：6