A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

被引:2
|
作者
Dai, Yanyun [1 ]
Yang, Yanfei [1 ]
Jiang, Nan [1 ]
Qi, Pengjia [1 ]
Chen, Qi [1 ]
Tong, Jijun [1 ]
机构
[1] Zhejiang Sci Tech Univ, Sch Informat Sci & Engn, Hangzhou 310018, Peoples R China
关键词
soft error; latch hardening; c-element; triple-node-upset; self-recoverable; TOLERANT;
D O I
10.3390/electronics11213606
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.
引用
收藏
页数:13
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