Reducing communication overhead in distributed logic simulation of VLSI circuits

Distributed simulation represents an attractive and smart way of improving the verification speed of large VLSI circuits. Unfortunately, this inexpensive approach suffers from the low performance of the communication networks used to connect local workstations. In this paper, we present a partitioning algorithm that attempts to find a suitable balance between the communication and the execution loan in a distributed simulator to enhance its speedup. The main features of this method are the use of logic replication to reduce the communication overhead and a realistic cost function that takes into account the activity of signals. Signals' activity can be obtained through a probabilistic evaluatation. A distributed simulator implementing a conservative synchronization method has been used to measure the efficiency of this algorithm.