Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer

被引：3

作者：

Chong, Eugene ^{[1
,2
]}

Kim, Bosul ^{[2
,3
]}

Lee, Sang Yeol ^{[4
]}

机构：

[1] Korea Inst Sci & Technol, Elect Mat Res Ctr, Seoul 136791, South Korea

[2] Univ Sci & Technol, Nanomat Sci & Engn, Seoul 305333, South Korea

[3] Elect & Telecommun Res Inst, Convergence Cpds & Mat Res Inst, Seoul 305700, South Korea

[4] Cheongju Univ, Dept Semicond Engn, Cheongju 360764, South Korea

来源：

E-MRS 2011 FALL SYMPOSIUM I: ADVANCES IN TRANSPARENT ELECTRONICS, FROM MATERIALS TO DEVICES III | 2012年 / 34卷

关键词：

STABILITY; TEMPERATURE;

D O I：

10.1088/1757-899X/34/1/012005

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A silicon-indium-zinc-oxide (SIZO) thin film transistor (TFT) with low channel-resistance (R-CH) indium-zinc-oxide (In2O3:ZnO = 9:1) buried layer annealed at low temperature of 200 degrees C exhibited high field-effect mobility (mu(FE)) over 55.8 cm(2)/V.s which is 5 times higher than that of the conventional TFTs due to small threshold voltage (V-th) change of 1.8 V under bias-temperature stress (BTS) condition for 420 minutes. The low-R-CH buried-layer allows more strong current-path formed in channel layer well within relatively high-R-CH channel-layer since it is less affected by the channel bulk and/or back interface trap with high carrier concentration.

引用

页数：6

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