Design of 2T XOR Gate Based Full Adder Using GDI Technique

被引：0

作者：

Kumar, Korra Ravi ^{[1
]}

Reddy, P. Mahipal ^{[1
]}

Sadanandam, M. ^{[1
]}

Kumar, Santhosh A. ^{[1
]}

Raju, M. ^{[1
]}

机构：

[1] Sree Chaitanya Coll Engn, Karimnagar, Telangana, India

来源：

2017 INTERNATIONAL CONFERENCE ON INNOVATIVE MECHANISMS FOR INDUSTRY APPLICATIONS (ICIMIA) | 2017年

关键词：

GDI; CMOS; XOR; XILINX; ARTIX7; BASYS3; PASS-TRANSISTOR LOGIC; CMOS; EXPRESSIONS; DELAY;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Full Adder is one of the fastest adder used in the complex data processing to perform fast arithmetic operations. The main aim of this paper is a design of 2T XOR gate based full adder using GDI technique. 2T XOR gate is an absolutely necessary primitive in the design of full adder. Intension behind a novel method of 2T XOR gate based Full adder design is to reduce power improve the speed with an optimized area by means of transistor count. GDI approach tend to provide the optimized conditions, the novel method is then applied to Full adder design. The entire work is carried out in the 180nm technology of LTspice tool is used for time delay, Xilinx 14.7 ISE, Basys3 Artix7 device is used for power analysis. The resulting analysis shows that the proposed method is better than conventional CMOS.

引用

页码：10 / 13

页数：4

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