A Reference-Less Single-Loop Half-Rate Binary CDR

被引：34

作者：

Jalali, Mohammad Sadegh ^{[1
]}

Sheikholeslami, Ali ^{[1
]}

Kibune, Masaya ^{[2
]}

Tamura, Hirotaka ^{[2
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

[2] Fujitsu Labs Ltd, Kawasaki, Kanagawa 2118588, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 09期

基金：

加拿大自然科学与工程研究理事会;

关键词：

Burst-mode CDR; clock and data recovery; cycle-slipping; frequency detection; gated VCO; DATA RECOVERY CIRCUIT; 10-GB/S CMOS CLOCK;

D O I：

10.1109/JSSC.2015.2429714

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a half-rate single-loop reference-less binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6x when it is activated.

引用

页码：2037 / 2047

页数：11

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