98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

被引：78

作者：

Fujishima, Minoru ^{[1
]}

Motoyoshi, Mizuki ^{[1
]}

Katayama, Kosuke ^{[1
]}

Takano, Kyoya ^{[1
]}

Ono, Naoko ^{[2
]}

Fujimoto, Ryuichi ^{[2
]}

机构：

[1] Hiroshima Univ, Grad Sch Adv Sci Matter, Higashihiroshima 7398530, Japan

[2] Semicond Technol Acad Res Ctr STARC, Yokohama, Kanagawa 2220033, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2013年 / 48卷 / 10期

基金：

日本科学技术振兴机构;

关键词：

CMOS; device model; millimeter wave; transceiver; 140; GHZ; AMPLIFIER; DEVICE; DESIGN; LINE;

D O I：

10.1109/JSSC.2013.2261192

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

引用

页码：2273 / 2284

页数：12

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