A low power and high linearity UWB low noise amplifier (LNA) for 3.1-10.6 GHz wireless applications in 0.13 μm CMOS process

In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1-10.6 GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13 mu m CMOS process. A gain of 19.5 +/- 1.5 dB within the entire band was exhibited. The simulated noise figure (NF) was 1-3.9 dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56 dBm while consuming 4.1 mW from a 0.6 power supply was achieved. The simulated input return loss (S-11) was less than -5 dB from 4.9 to 12.1 GHz. The output return loss (S-22) was below -10.6 dB and S-12 was better than -70.6 dB. (C) 2013 Elsevier Ltd. All rights reserved.