Privatizing transactions for Lee's algorithm in commercial hardware transactional memory

被引:2
作者
Quislant, Ricardo [1 ]
Gutierrez, Eladio [1 ]
Zapata, Emilio L. [1 ]
Plata, Oscar [1 ]
机构
[1] Univ Malaga, Dept Comp Architecture, E-29071 Malaga, Spain
关键词
Hardware transactional memory; Lee's algorithm; Early release; Open transactions; Lazy subscription;
D O I
10.1007/s11227-017-2188-2
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Lee's algorithm solves the path-connection problems that arise in logical drawing, wiring diagramming or optimal route finding. Its parallel version has been widely used as a benchmark to test transactional memory systems. It exhibits transactions of large size and duration that stress these systems exposing their limitations. In fact, Lee's algorithm has been proved to perform similar to sequential in commercial hardware transactional memory systems due to persistent capacity overflows. In this paper, we propose a novel approach to Lee's algorithm in the context of commercial hardware transactional memory systems. We show how the majority of the computation of the largest transaction, i.e. grid privatization and path calculation, can be executed out of the boundaries of the transaction, thus reducing the size requirements. We leverage the correctness criteria of lazy subscription fallback locks to ensure a correct execution. This novel approach uses transactional memory extensions from commercial processors from a different point of view, not needing either early release or open-nested transaction features that are not yet implemented in these systems. We propose an application programming interface to facilitate the task of the programmer. Experiments are carried out with the Intel Core and IBM Power8 architectures, showing speedups around 3.5 over both the standard transactional version of the algorithm and the sequential for certain grid inputs and four threads. We also compare our proposal with a software transactional memory LeeTM approach.
引用
收藏
页码:1676 / 1694
页数:19
相关论文
共 26 条
[1]  
[Anonymous], 2014, P 9 WORKSH T COMP
[2]  
[Anonymous], 3 WORKSH T COMP TRAN
[3]  
[Anonymous], INT C HIGH PERF COMP
[4]  
[Anonymous], TECH REP
[5]  
[Anonymous], IEEE COMPUT ARCHIT L
[6]  
Ansari M, 2008, LECT NOTES COMPUT SC, V5022, P196, DOI 10.1007/978-3-540-69501-1_21
[7]   Weighted adaptive concurrency control for software transactional memory [J].
Ansari, Mohammad .
JOURNAL OF SUPERCOMPUTING, 2014, 68 (03) :1027-1047
[9]  
Cain HaroldW., 2013, Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA'13, P225, DOI DOI 10.1145/2485922.2485942
[10]   A priority scheduling for TM pathologies [J].
Chen, Chia-Jung ;
Chang, Rong-Guey .
JOURNAL OF SUPERCOMPUTING, 2015, 71 (03) :1095-1115