On-chip Monitors of Supply Noise Generated by System-level ESD

被引:0
|
作者
Thomson, Nicholas [1 ,2 ]
Reiman, Collin [1 ]
Xiu, Yang [1 ]
Rosenbaum, Elyse [1 ]
机构
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
[2] Intel Corp, 2501 NE Century Blvd, Hillsboro, OR 97124 USA
来源
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2017年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Two supply noise monitor circuits are demonstrated on a 130-nm test chip. These monitors are capable of providing quantitative measurements of on-chip supply voltage perturbations resulting from system-level ESD. Circuit-level simulations reproduce all trends found in the measurement results.
引用
收藏
页数:10
相关论文
共 50 条
  • [31] Layout optimization of GGISCR structure for on-chip system level ESD protection applications
    Zeng, Jie
    Dong, Shurong
    Wong, Hei
    Hu, Tao
    Li, Xiang
    SOLID-STATE ELECTRONICS, 2016, 126 : 152 - 157
  • [32] Incorporating PVT variations in system-level power exploration of on-chip communication architectures
    Pasricha, Sudeep
    Park, Young-Hwan
    Kurdahi, Fadi J.
    Dutt, Nikil
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 363 - 370
  • [33] A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation
    Tanzawa, Toru
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (12) : 2351 - 2355
  • [34] A System-level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping
    Diamantopoulos, Dionysios
    Hagleitner, Christoph
    2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018), 2018, : 341 - 344
  • [35] Is system-level ESD testing valid for ICs?
    Robinson-Hahn, Donna
    Power Electronics Technology, 2008, 34 (09): : 26 - 29
  • [36] Bright 3D Display, Native and Integrated On-Chip or System-Level
    Ellwood, Sutherland C., Jr.
    THREE-DIMENSIONAL IMAGING, VISUALIZATION, AND DISPLAY 2011, 2011, 8043
  • [37] Circuit design techniques for on-chip power supply noise monitoring system
    Chen, H
    Hsu, L
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2005, 3728 : 704 - 713
  • [38] Modeling Power Supply Noise Effects for System-Level Simulation of ΔΣ-ADCs
    Meier, Jonas
    Speicher, Fabian
    Beyerstedt, Christoph
    Saalfeld, Tobias
    Boronowsky, Gregor
    Wunderlich, Ralf
    Heinen, Stefan
    2019 16TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2019), 2019, : 265 - 268
  • [39] On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress
    Caignet, F.
    Nolhier, N.
    Bafleur, M.
    Wang, A.
    Mauran, N.
    MICROELECTRONICS RELIABILITY, 2013, 53 (9-11) : 1278 - 1283
  • [40] System-level PVT Variation-Aware Power Exploration of On-Chip Communication Architectures
    Pasricha, Sudeep
    Park, Young-Hwan
    Dutt, Nikil
    Kurdahi, Fadi J.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2009, 14 (02)