Improving the Reliability of Embedded Memories using ECC and Built-In Self-Repair Techniques

被引：0

作者：

Manasa, R. ^{[1
]}

Hegde, Ganapathi ^{[1
]}

Vinodhini, M. ^{[1
]}

机构：

[1] Amrita Vishwa Vidhyapeetham, Amrita Sch Engn, Dept ECE, Vengal, India

来源：

2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018) | 2018年

关键词：

Built-In Self-Test (BIST); Built-In Redundancy Analysis (BIRA); Built-In Self Repair (BISR); Soft Errors; Hard Errors; Error Correction Codes (ECCs); Reliability;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

System on Chip (SoC) process technology is shrinking day by day resulting in increased complexity. In the presence of faults, the reliability of embedded memories in deep submicron technology is becoming a significant challenge. Embedded Memories are highly prone to soft errors and hard faults. Hence, hard repair techniques combined with Error Correction Codes (ECCs) can improve the reliability of embedded memories. An integrated ECC and Built-In Self-Repair (BISR) technique is proposed in this paper can correct 8 faulty bits for a 16-bit input. Higher error correction and repair capability gives the higher reliability. The proposed integrated ECC and BISR has less area and more faulty bit correction capability compared to Enhanced Built -In Self-Repair (EBISR) technique.

引用

页码：1436 / 1439

页数：4

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