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- [1] FPGA IMPLEMENTATION OF HIGH SPEED VEDIC MULTIPLIER USING CSLA FOR PARALLEL FIR ARCHITECTURE 2014 2ND INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS), 2014,
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- [3] A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification 2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2009, : 24 - 31
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- [7] FPGA Implementation of a High Speed VLSI Architecture for CORDIC TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2009, : 2054 - 2058
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- [9] A HIGH SPEED CONFIGURABLE FPGA ARCHITECTURE FOR BILATERAL FILTERING 2014 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP), 2014, : 1248 - 1252