50% PAE 20-mA quiescent current W-CDMA power amplifier with on-chip dynanuic-gain linearizer

被引:9
|
作者
Aoki, Y [1 ]
Yamanouchi, S [1 ]
Kunihiro, K [1 ]
Miyazaki, T [1 ]
Hirayama, T [1 ]
Hida, H [1 ]
机构
[1] NEC Corp Ltd, Syst Devices Res Labs, Kawasaki, Kanagawa 2118666, Japan
来源
2006 IEEE RADIO AND WIRELESS SYMPOSIUM, PROCEEDINGS | 2006年
关键词
amplifier distortion; average power efficiency; interchannel interference; intermodulation distortion; MMIC power amplifiers; wideband code-division multiple access;
D O I
10.1109/RWS.2006.1615142
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper explains a power-effective linearization technique for power amplifiers (PAs) having gain-expansion characteristics. A new on-chip dynamic-gain-deviation cancellation circuit improves the adjacent-channel-leakage-power ratio (ACLR) for a W-CDMA signal by 11 dB. At a supply of 3.5 V and an output power of 26.9 dBm, a fabricated PA with a quiescent current (Iq) of 19 mA exhibited a power-added efficiency of 50%, a gain of 26 dB, and an ACLR of -40 dBc. Furthermore, when we applied this technique to a PA with Iq of only 10-mA, this PA also satisfied the W-CDMA criteria.
引用
收藏
页码:251 / 254
页数:4
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